fn8083 rev 1.00 page 1 of 9 august 27, 2015 fn8083 rev 1.00 august 27, 2015 isl95310 digitally controlled potentiometer (xdcp?), terminal voltage 0v to 13.2v, 128 taps up/down interface datasheet the intersil isl95310 is a digi tally controlled potentiometer (xdcp). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by an up/down interface. the potentiometer is impleme nted by a resistor array composed of 127 resistive el ements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the wiper of each potentiometer has an associat ed volatile wiper counter register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr con trols the position o f the wiper on the resistor array through the swit ches. at power-up, the device recalls the contents of the default data r egisters to the corresponding wr. the positi on of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonv olatile memory and then be recalled upon a subseq uent power-up operation. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including: ? lcd contrast control ? parameter and bias adjustments ? mechanical potentiometer replacement ? industrial and aut omotive control features ? non-volatile solid-s tate potentiometer ? up/down interface wit h chip select enable ? dcp terminal voltage, 0 to +13.2v ? 128 wiper tap points - 0.8% resolution - wiper position stored i n nonvolatile memory and recalled on power-up ? 127 resistive elements - temperature compensated - low wiper resistance 70 ? typical @ 3.3v ? low power cmos - standby current, 2a at v cc = +3.6v ? high reliability - endurance, 200,000 data changes per bit - register data retention 50 years @ t ? 75c ?r total values = 10k ??? 50k ? ? 10-lead msop package - pb-free plus anneal available (rohs compliant) pinout isl95310 (10 ld msop) top view ordering information part number resistance option ( ? ) temp range (c) package (rohs compliant) isl95310wiu10z (see note) (no longer available, recommended replacement: ISL95310UIU10Z-tk) 10k -40 to +85 10 ld msop ISL95310UIU10Z (see note) 50k -40 to +85 10 ld msop add -tk suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/ die attach materials and 100% matte tin plate termination finish , which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. v cc inc u/d gnd 1 2 3 4 10 9 8 7 r h r w nc v+ 5 r l 6 cs
isl95310 fn8083 rev 1.00 page 2 of 9 august 27, 2015 block diagram 7-bit up/down counter 7-bit nonvolatile memory store and recall control circuitry one of 128 decoder resistor array r h u/d inc cs transfer gates r l r w control and memory up/down (u/d ) increment (inc ) device select (cs ) v+ gnd r h r w r l simple block diagram detailed block diagram 0 1 2 124 125 126 127 vcc pin number symbol description 1u/d controls the direction of wiper movement and whether the counte r is incremented or decremented 2 gnd ground 3v cc positive logic supply voltage 4cs chip select; the device is selected when the cs input is low; also used to initiate a nonvolatile store 5 nc no connect; pin is to be left unconnected 6r h a fixed terminal for one end of the potentiometer resistor 7r w the wiper terminal whi ch is equivalent to the movable terminal of a potentiometer 8r l a fixed terminal for one end of the potentiometer resistor 9 v+ positive bias voltage for t he potentiometer wiper control 10 inc increment input; negative edge triggered
isl95310 fn8083 rev 1.00 page 3 of 9 august 27, 2015 absolute maximum ratings reco mmended operating conditions storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on cs , inc , u/d with respect to gnd . . . . . . . . . . . . . . . . . . . . -0.3 v to v cc +0.3v voltage on v+ (referenced to gnd) . . . . . . . . . . . . . . . . . . . . +13.2v ? v = |v (rh) -v (rl) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ r h , r l , r w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v power rating of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mw temperature range (industrial) . . . . . . . . . . . . . . . . . -40c to +85c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v v+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v to 13.2v wiper current of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. analog specifications over recommended operating condit ions unless otherwise stated. symbol parameter test conditions min typ (note 1) max unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % v rh r h terminal voltage v rl = 0v 0 v+ v r w wiper resistance v+ = 12v , wiper current = v+ / r total 70 200 ? c h /c l /c w potentiometer capacitance (note 13) 10/10/ 25 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v+ 0.1 1 a voltage divider mode (0v @ r l ; v+ @ r h ; measured at r w , unloaded) inl (note 6) integral non-linearity -1 1 lsb (note 2) dnl (note 5) differential non-linearity w option -0.75 0.75 lsb (note 2) u option -0.5 0.5 zserror (note 3) zero-scale error u option 0 1 7 lsb (note 2) w option 0 0.5 2 fserror (note 4) full-scale error u option -7 -1 0 lsb (note 2) w option -2 -1 0 tc v (note 7) ratiometric temperatur e coefficient dcp register set to 40 hex 4 ppm/c resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 11) integral non-linearity dcp register set between 20 hex and 7f he x; monotonic over all tap positions -1 1 mi (note 8) rdnl (note 10) differential non-linearity w option -0.75 0.75 mi (note 8) u option -0.5 0.5 roffset (note 9) offset dcp register set to 00 hex, w option 0 1 7 mi (note 8) dcp register set to 00 hex, u option 0 0.5 2 mi (note 8) tc r (note 12) resistance temperature coefficient dcp register set between 20 h ex and 7f hex 45 ppm/c
isl95310 fn8083 rev 1.00 page 4 of 9 august 27, 2015 operating specifications over the recommended operating conditions unless otherwise spec ified. symbol parameter test conditions min typ (note 1) max unit i cc1 v cc supply current, volatile write/read cs = v il , u/d = v il or v ih and inc = 0.4v/2.4v min; t cyc r l , r h , r w not connected 1ma i cc2 v cc supply current, nonv olatile write cs = v il , u/d = v il or v ih and inc = 0.4v/2.4v min; t cyc r l , r h , r w not connected 3ma i sb v cc current, standby v cc = +5.5v, 2-wire interface in standby state 5 a v cc = +3.6v, 2-wire interface in standby state 2 a i v+ v+ bias current v+ = 13.2v; v cc = +5.5v 1 a i lkgdig leakage current, at pins inc , cs , u/d , a0, and a1 pins voltage at pin from gnd to v cc -10 10 a i li cs input leakage current v in = v cc 1 a v cc = 3v, cs = 0 60 100 150 a v cc = 5v, cs = 0 120 200 250 a i v+ v+ bias current v+ = 13.2v; v cc = +5.5v 1 a t dcp (note 13) dcp wiper response time inc falling edge of last bit of dcp data byte to wiper change 1s vpor (note 13) power-on recall voltage minimum v cc at which memory recall occurs 1.8 2.6 v v cc ramp (note 13) v cc ramp rate 0.2 v/ms t d (note 13) power up delay v cc above vpor, to dcp ini tial value register recall completed, and 2-wire interface in standby state 3ms eeprom specs eeprom endurance 150,000 cycles eeprom retention temperature ? 75c 50 years serial interface specs v il inc , cs , and u/d -0.3 0.3* v cc v v ih inc , cs , and u/d 0.7* v cc v cc + 0.3 v hysteresis (note 13) inc , cs , and u/d input buffer hysteresis 0.05* v cc v cpin (note 13) inc , cs , and u/d pin capacitance 10 pf ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated symbol parameter min typ (note 4) max unit t cl cs to inc setup 100 ns t ld (note 13) inc high to u/d change 100 ns t di (note 13) u/d to inc setup 1 s t ll inc low period 1 s t lh inc high period 1 s t lc inc inactive to cs inactive 1 s
isl95310 fn8083 rev 1.00 page 5 of 9 august 27, 2015 symbol table t cphs cs deselect time (store) 20 ms t cphns (note 13) cs deselect time (no store) 1 s t iw (note 13) inc to r w change 100 500 s t cyc inc cycle time 4 s t r , t f (note 13) inc input rise and fall time 500 s notes: 1. typical values are for t a = 25c and 3.3v supply voltage. 2. lsb: [v(r w ) 127 C v(r w ) 0 ]/127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 3. zs error = v(r w ) 0 /lsb. 4. fs error = [v(r w ) 127 C v+]/lsb. 5. dnl = [v(r w ) i C v(r w ) i-1 ]/lsb-1, for i = 1 to 127. i is the dcp register setting. 6. inl = v(r w ) i C (i ? lsb C v(r w ) 0 ) for i = 1 to 127. 7. for i = 16 to 120 decimal, t = -40c to 85c. max( ) is the max imum value of the wiper voltage and min ( ) is the minimum valu e of the wiper voltage over the temperature range. 8. mi = | r 127 C r 0 | /127. r 127 and r 0 are the measured resistances for the dcp register set to 7f he x and 00 hex respectively. 9. roffset = r 0 /mi, when measuring between r w and r l . roffset = r 127 /mi, when measuring between r w and r h . 10. rdnl = (r i C r i-1 )/mi, for i = 16 to 127. 11. rinl = [r i C (mi ? i) C r 0 ]/mi, for i = 16 to 127. 12. for i = 16 to 127, t = -40c to 85c. max( ) is the maximum val ue of the resistance and min ( ) is the minimum value of the re sistance over the temperature range. 13. this parameter is not 100% tested. 14. t wc is the minimum cycle time to be allowed for any non-volatile w rite by the user, unless acknowl edge polling is used. it is the time from a valid stop condition at the end of a write sequence of a 3-wire serial interface write operation, to the end of the self-timed internal non-volatile write cycle. ac electrical specifications v cc = 5v 10%, t a = full operating temperature range unless otherwise stated (continued) symbol parameter min typ (note 4) max unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 --------------------------------------------------------------- --------------------------------- -x 10 6 125c ---------------- - = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 --------------------------------------------------------------- --- 10 6 125c ---------------- - ? = waveform inputs outputs must be steady will be steady may change from low to high will change from low to high will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance may change from high to low
isl95310 fn8083 rev 1.00 page 6 of 9 august 27, 2015 a.c. timing power up and down requirements in order to prevent unwanted tap position changes, or an inadvertent store, bring the cs and inc high before or concurrently with the v cc pin on power-up. the potentiometer voltages must be applied after this sequence is completed. during power-up, the data sheet parameters for the dcp do not fully apply until 1ms after v cc reaches its final value. the v cc ramp spec is always in effect. pin descriptions r h and r l the high (r h ) and low (r l ) terminals of the isl95310 are equivalent to the fixed t erminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is det ermined by the control inputs. up/down (u/d ) the u/d input controls the direct ion of the wiper movement and whether the counter is decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indica ted by the logic level on the u/d input. chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is compl ete the isl9531 0 will be placed in the low power standby mode u ntil the device is selected once again. principles of operation there are three sections of the isl95310: the input control, counter and decode section ; the nonvolatile memory; and the resistor array. the input cont rol section operates just lik e an up/down counter. the output o f this counter is decoded to turn on a single electronic sw itch connecting a point on the resistor array to the wiper output. under the proper conditions the contents of t he counter can be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 127 indiv idual resistors connected in series. at either end of the arra y and between e ach resistor is an electronic swit ch that transfers t he potential at that point to the wiper. the wiper, when at either fixe d terminal, act s like its mechanical equivalent and does not move bey ond the last position. that is, the counte r does not wrap around when clocked to either extreme. the electronic switches on the device operat e in a make before break mode when the wiper changes tap positions. if the wiper is moved several pos itions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved seve ral positions. when the device is powered-dow n, the last wiper position stored will be maintained in t he nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. cs inc u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns
isl95310 fn8083 rev 1.00 page 7 of 9 august 27, 2015 on applying power to the isl95310, the v cc supply should have a monotonic ramp to the specified operating voltage. it is important that once v cc reaches 1v that it increases to at least 2.5v in less than 7.5ms (0.2v/ms). the ramp rate before and after these thresholds is not important. v cc must be applied prior to, or simultaneously, with v+. under no condition should v+ be applied without v cc . while the sequence of applying v+ and v cc to the isl95310 does not affect the proper recall of the wiper position, applying v+ before v cc powers the electronic switches of the dcp before the electronic switch control signals are applied. this can result in multiple electronic switches being turned on, which could load the power supply and cause brief, unexpected potentiomet er wiper settings. to prevent unknown wiper positions on the isl95310 on power down, it is recommended that v+ turn off before or simultaneously with v cc . if v+ remains on after v cc turns off, the wiper position can remain unchanged from its previous setting or it can go to an undefined state. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a seven bit counter. the output of this counter is decoded to select one of one hundred wiper positi ons along the resistive array. the value of the counter is st ored in nonvolatile memory whenever cs transitions high while the inc input is also high. the system may select the isl95310, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as describ ed above and once the new position is reached, the syst em must keep inc low while taking cs high. the new wiper positi on will be maintained until changed by the syste m or until a powe r-up/down cycle recalled the previously stored data. this procedure allows the system to alwa ys power-up to a preset value stored in nonv olatile memory; then during system operation minor adjust ments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. during initial power-up cs must go high along with or before v cc to avoid an accidental store generation. table 1. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current l x no store, return to standby h h x standby l h wiper up one position (not recommended) l l wiper down one position (not recommended)
fn8083 rev 1.00 page 8 of 9 august 27, 2015 isl95310 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2005-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision . date revision change august 27, 2015 fn8083.1 - ordering information table on page 1. - added revision history. - added about intersil verbiage. -updated pod m10.118 to most cur rent version change is as follo ws: added land pattern.
isl95310 fn8083 rev 1.00 page 9 of 9 august 27, 2015 package outline drawing m10.118 10 lead mini small outline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
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